pytc.solver.test.test_kmat_tile_parity¶

Tile-size parity gate for the K1/K3 ISDF build.

Tiling is a blocking parameter (a device-memory lever), never a numerical input: r2/host tile boundaries change only the scan accumulation order (FP reassociation). Forced small tiles must therefore reproduce the default auto-sized tiles to reassociation level, gated at 1e-12 relative – beyond that, a difference is a real defect, not a tile effect.

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